Equalizers are an important element in many diverse digital information applications, such as voice, data, and video communications. These applications employ a variety of transmission media. Although the various media have differing transmission characteristics, none of them is perfect. That is, every medium induces variation into the transmitted signal, such as frequency-dependent phase and amplitude distortion, multi-path reception, other kinds of ghosting, such as voice echoes, and Rayleigh fading. In addition to channel distortion, virtually every sort of transmission also suffers from noise, such as additive white gausian noise (xe2x80x9cAWGNxe2x80x9d). Equalizers are therefore used as acoustic echo cancelers (for example in full-duplex speakerphones), video deghosters (for example in digital television or digital cable transmissions), signal conditioners for wireless modems and telephony, and other such applications.
One important source of error is intersymbol interference (xe2x80x9cISIxe2x80x9d). ISI occurs when pulsed information, such as an amplitude modulated digital transmission, is transmitted over an analog channel, such as, for example, a phone line or an aerial broadcast. The original signal begins as a reasonable approximation of a discrete time sequence, but the received signal is a continuous time signal. The shape of the impulse train is smeared or spread by the transmission into a differentiable signal whose peaks relate to the amplitudes of the original pulses. This signal is read by digital hardware, which periodically samples the received signal.
Each pulse produces a signal that typically approximates a sinc wave. Those skilled in the art will appreciate that a sinc wave is characterized by a series of peaks centered about a central peak, with the amplitude of the peaks monotonically decreasing as the distance from the central peak increases. Similarly, the sinc wave has a series of troughs having a monotonically decreasing amplitude with increasing distance from the central peak. Typically, the period of these peaks is on the order of the sampling rate of the receiving hardware. Therefore, the amplitude at one sampling point in the signal is affected not only by the amplitude of a pulse corresponding to that point in the transmitted signal, but by contributions from pulses corresponding to other bits in the transmission stream. In other words, the portion of a signal created to correspond to one symbol in the transmission stream tends to make unwanted contributions to the portion of the received signal corresponding to other symbols in the transmission stream.
This effect can theoretically be eliminated by proper shaping of the pulses, for example by generating pulses that have zero values at regular intervals corresponding to the sampling rate. However, this pulse shaping will be defeated by the channel distortion, which will smear or spread the pulses during transmission. Consequently, another means of error control is necessary. Most digital applications therefore employ equalization in order to filter out ISI and channel distortion.
Generally, two types of equalization are employed to achieve this goal: automatic synthesis and adaptation. In automatic synthesis methods, the equalizer typically compares a received time-domain reference signal to a stored copy of the undistorted training signal. By comparing the two, a time-domain error signal is determined that may be used to calculate the coefficient of an inverse function (filter). The formulation of this inverse function may be accomplished strictly in the time domain, as is done in Zero Forcing Equalization (xe2x80x9cZFExe2x80x9d) and Least Mean Square (xe2x80x9cLMSxe2x80x9d) systems. Other methods involve conversion of the received training signal to a spectral representation. A spectral inverse response can then be calculated to compensate for the channel distortion. This inverse spectrum is then converted back to a time-domain representation so that filter tap weights can be extracted.
In adaptive equalization the equalizer attempts to minimize an error signal based on the difference between the output of the equalizer and the estimate of the transmitted signal, which is generated by a xe2x80x9cdecision device.xe2x80x9d In other words, the equalizer filter outputs a sample, the decision device determines what value was most likely transmitted, and the adaptation logic attempts to keep the difference between the two small. The main idea is that the receiver takes advantage of the knowledge of the discrete levels possible in the transmitted pulses. When the decision device quantizes the equalizer output, it is essentially discarding received noise. A crucial distinction between adaptive and automatic synthesis equalization is that adaptive equalization does not require a training signal.
Error control coding generally falls into one of two major categories: convolutional coding and block coding (such as Reed-Solomon and Golay coding). At least one purpose of equalization is to permit the generation of a mathematical xe2x80x9cfilterxe2x80x9d that is the inverse function of the channel distortion, so that the received signal can be converted back to something more closely approximating the transmitted signal. By encoding the data into additional symbols, additional information can be included in the transmitted signal that the decoder can use to improve the accuracy of the interpretation of the received signal. Of course, this additional accuracy is achieved either at the cost of the additional bandwidth necessary to transmit the additional characters, or of the additional energy necessary to transmit at a higher frequency.
A convolutional encoder comprises a K-stage shift register into which data is clocked. The value K is called the xe2x80x9cconstraint lengthxe2x80x9d of the code. The shift register is tapped at various points according to the code polynomials chosen. Several tap sets are chosen according to the code rate. The code rate is expressed as a fraction. For example, a xc2xd rate convolutional encoder produces an output having exactly twice as many symbols as the input. Typically, the set of tapped data is summed modulo-2 (i.e., the XOR operation is applied) to create one of the encoded output symbols. For example, a simple K=3, xc2xd rate convolutional encoder might form one bit of the output by modulo-2-summing the first and third bits in the 3-stage shift register, and form another bit by modulo-2-summing all three bits.
A convolutional decoder typically works by generating hypotheses about the originally transmitted data, running those hypotheses through a copy of the appropriate convolutional encoder, and comparing the encoded results with the encoded signal (including noise) that was received. The decoder generates a xe2x80x9cmetricxe2x80x9d for each hypothesis it considers. The xe2x80x9cmetricxe2x80x9d is a numerical value corresponding to the degree of confidence the decoder has in the corresponding hypothesis. A decoder can be either serial or parallelxe2x80x94that is, it can pursue either one hypothesis at a time, or several.
One important advantage of convolutional encoding over block encoding is that convolutional decoders can easily use xe2x80x9csoft decisionxe2x80x9d information. xe2x80x9cSoft decisionxe2x80x9d information essentially means producing output that retains information about the metrics, rather than simply selecting one hypothesis as the xe2x80x9ccorrectxe2x80x9d answer. For an overly-simplistic example, if a single symbol is determined by the decoder to have an 80% likelihood of having been a xe2x80x9c1xe2x80x9d in the transmission signal, and only a 20% chance of having been a xe2x80x9c0xe2x80x9d, a xe2x80x9chard decisionxe2x80x9d would simply return a value of 1 for that symbol. However, a xe2x80x9csoft decisionxe2x80x9d would return a value of 0.8, or perhaps some other value corresponding to that distribution of probabilities, in order to permit other hardware downstream to make further decisions based on that degree of confidence.
Block coding, on the other hand, has a greater ability to handle larger data blocks, and a greater ability to handle burst errors.
FIG. 1 illustrates a block diagram of a typical digital communication receiver, including channel coding and equalization, indicated generally at 100. The receiver 100 comprises a demodulation and sync component 110, which converts the received analog signal back into a digital format. The receiver 100 further comprises an equalizer 120, an inner decoder 130, a de-interleaver 140, and an outer decoder 150. The inner coding is typically convolutional coding, while the outer coding is typically block coding, most often Reed-Solomon coding. The convolutional and block coding are generally combined in order to exploit the complementary advantages of each.
FIG. 2 is a diagram of an equalizer 120 such as is commonly used in the digital receiver 100 shown in FIG. 1. Typically, the equalizer 120 includes a controller 228, a finite impulse response (xe2x80x9cFIRxe2x80x9d) filter 222, a decision device 226, and a decision feedback equalizer (xe2x80x9cDFExe2x80x9d) 224. The FIR filter 222 receives the input signal 221. The FIR filter 222 is used to cancel pre-ghostsxe2x80x94that is, ghost signals that arrive before the main transmission signal. The decision device 226 examines its inputs and makes a decision as to which one of the received signals at its input is the signal to be transmitted to the output 229. The input to the decision device 226 is modified by a decision feedback equalizer 224, which is used to cancel post-ghostsxe2x80x94that is, ghost signals that arrive after the main transmission signalxe2x80x94and the residual signal generated by the FIR filter 222.
The decision device 226 is typically a hard decision device, such as a slicer. For example, in an 8 VSB system, the slicer can be a decision device based upon the received signal magnitude, with decision values of 0, xc2x12, xc2x14, and xc2x16, in order to sort the input into symbols corresponding to the normalized signal values of xc2x11, xc2x13, xc2x15, and xc2x17. For another example, the slicer can be multi-dimensional, such as those used in quadrature amplitude modulation (xe2x80x9cQAMxe2x80x9d) systems.
The controller 228 receives the input data and the output data and generates filter coefficients for both the FIR filter 222 and the decision feedback filter 224. Those skilled in the art will appreciate that there are numerous methods suitable for generating these coefficients, including LMS and RLS algorithms.
FIG. 3 illustrates further details of the equalizer 120 shown in FIG. 2. The input to the decision feedback equalizer 224 is output from the decision device 226, such as a slicer. The input data is delayed (F+M) stages, where F equals the number of stages in the FIR filter 222 and M equals the number of stages in the decision feedback equalizer 224. The equalizer 120 then passes the equalized data to a trellis decoder 350. An error signal 310 is generated by subtracting the input to the slicer 226 from its output. The error signal 310 is multiplied by a step size 320 before it is used to update the tap coefficients. Typically, the step size 320 is less than one, in order to permit the error signal to iteratively adjust the coefficient taps over multiple cycles, so that variations in channel response and noise are averaged out. Generally, the smaller the step size, the more severe the transient conditions under which the equalizer 120 can converge, though at the cost of slower convergence.
FIG. 4 shows the further details of a trellis encoder, shown generally at 400, suitable for use with the decision feedback equalizer 224 shown in FIG. 3. The trellis encoder 400 is the 8 VSB trellis encoder, precoder, and symbol mapper. As will be known by those skilled in the art, the 8 VSB trellis encoder 400 uses an 8-level, 3-bit, one dimensional constellation. As can be seen from FIG. 4, the 8 VSB trellis encoder 400 uses a ⅔ rate trellis code.
Typically, the trellis decoder 350 uses a Viterbi algorithm to decode the signal encoded by the 8 VSB trellis encoder 400. Typically, the trellis decoder 350 has a large number of stagesxe2x80x94most often 16 or 24. The decoded output 229 is de-interleaved by the de-interleaver 140, and then sent to the outer decoder 150.
FIG. 5 shows a typical trellis diagram for an 8 VSB trellis code with n stages, shown generally at 500. The heavier line illustrates a current survive path. At each decoding clock cycle a new symbol is sent to the trellis decoder and the survive path is renewed. It will be appreciated that in a VSB system each sample contains one symbol, while in QAM or offset-QAM systems, each sample contains two symbolsxe2x80x94one in the I channel, the other in the Q channel. However, regardless of the sample size, the coding and decoding is always performed symbol by symbol. At each stage a decision is made about which state is the most likely (i.e., which symbol was most likely transmitted), based on the survive path. For example, stage 1 gives the first estimation to the input, and stage 2 gives the second estimation to the input, etc. It will be appreciated that the survive path may change based on the decoding process as each new input symbol is received, so that the survive path may not be the same (though shifted one symbol) from one input sample time to another.
FIG. 6 shows the decoding error rate using a typical trellis decoder with the Viterbi decoding algorithm. As can be seen from the graph, while the system is running at the threshold, or even slightly below it, the error rate is lower after decoding, and the greater the number of decoding stages, the lower the error rate. It can also be seen that the error rate decreases greatly as the signal-to-noise ratio increases. Note that the threshold shown is the boundary in an 8 VSB system where the bit error rate after Reed-Solomon decoding is one in 106.
It will be appreciated that the equalizer 120 cannot converge if the decision device 226 makes too many errors. For example, it is believed that if a slicer 226 has an error rate greater than about 0.1 the equalizer will not converge. Therefore, at start up, when there are large channel distortions, equalizer 120 cannot start to work. It has to use training signals, if available, to compensate for the channel distortion, or use a different type of algorithm, such as blind equalization, to converge. Using the training signals alone, or in combination with blind equalization may still not be sufficient to converge. Even if they are sufficient, it can be difficult to determine this fact, or at what point the compensation becomes acceptable. Furthermore, in blind equalization methods the feedback portion of the equalizer 120 is not based on decisions from the decision device 226, and therefore a much higher resolution is required. Consequently, hardware that is substantially more complex may be required.
Those skilled in the art will also appreciate that during operation of an equalizer 120 it is desirable to reduce the step size when the signal-to-noise ratio is lower. To achieve that end, a stop-and-go algorithm could be used to stop the DFE 224 when the signal-to-noise ratio falls below some threshold. However, it can be difficult to determine the signal-to-noise ratio from instant to instant during operation. Therefore, most systems employing such an algorithm improve performance only under certain circumstances, and at the cost of poorer performance under other conditions.
What is needed is an equalizer in which the step size is adjusted in relation to the error rate from the decision device. The present invention is directed towards meeting these needs, as well as providing other advantages over prior equalizers.
A first embodiment adaptive equalizer comprises: a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
A second embodiment adaptive equalizer comprises: a slicer; a decision feedback equalizer coupled to the slicer; an FIR filter coupled to the decision device; and a Viterbi decoder coupled to the decision device, adapted to provide a eliability output and a decoded output. The Viterbi decoder determines the reliability output by generating a soft output from each decoding stage of the Viterbi decoder, each soft output being equal to the difference between an accumulated metric of a survive path and a deleted path for the decoding stage, the soft output of a final decoding stage being used as the reliability output. An error signal is generated by subtracting an output of the equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
A third embodiment adaptive equalizer comprises: a decision device; an FIR filter coupled to the decision device; a decision feedback equalizer coupled to the decision device; and a trellis decoder coupled to the decision device and adapted to produce a reliability output and a decoded output. The error signal is generated by subtracting a delayed output of the equalizer from an output of the trellis decoder. A magnitude of change in the coefficients is selected based at least in part upon the reliability output.
A fourth embodiment adaptive equalizer comprises: a slicer; an FIR filter coupled to the slicer; a DFE coupled to the slicer; a Viterbi decoder coupled to the decision device and adapted to produce a reliability output and a decoded output; and a mapper coupled to receive the decoded output of the Viterbi decoder and to generate a mapped and scaled output. The error signal is generated by delaying an output of the DFE by a number of cycles equal to a number of cylces the Viterbi decoder uses to generate the reliability output and subtracting the delayed output of the DFE from an output of the Viterbi decoder. A magnitude of change in the coefficients is selected based at least in part upon the reliability output and at least in part upon the error signal.